Generally, various advanced processes and techniques may be employed in design and fabrication of IC devices, particularly to aid with reducing the geometries of components and structures utilized to scale down IC devices beyond 7 nm. A NS FET may employ a stack of NS structures (e.g. horizontal semiconductor sheets) as gated conduction channels between source/drain (S/D) regions of the transistor, wherein the gate surrounds, i.e. gate-all-around (GAA), a gate region of each NS structure in the transistor. However, the reduced spaces between the NS structures present challenging steps for the traditional processes.
FIG. 1A illustrates a NS FET including NS structures 101, gate structures 103, and S/D regions 105 and 107. FIG. 1B illustrates a cross-sectional view along a cross-sectional plane 1B of FIG. 1A, wherein a gate structure 103 is a GAA surrounding a gate region 109 of each NS structure 101.
FIGS. 1C through 1F illustrate the conventional process for forming the structure of FIGS. 1A and 1B. Adverting to FIG. 1C, a gate dielectric layer 111 is illustrated surrounding the gate regions of the NS structures 101. FIG. 1D illustrates formation of gate metal layers 113 such as titanium nitride (TiN) formed by atomic layer deposition (ALD) surrounding the gate dielectric layers 111 of the NS structures 101. An annealing barrier layer 115 (e.g. silicon (Si)) is formed by chemical vapor deposition (CVD) surrounding the gate metal layers 113 as well as filling spaces 117 between adjacent NS structures 101. Spaces 117 may be less than 5 nanometers (nm).
In FIG. 1E, after an annealing process, the barrier layer 115 and the gate metal layers 113 are removed to expose the annealed gate dielectric layer 119 surrounding each gate area of the NS structures 101. However, as illustrated, some sections of the gate metal layers 113 and the barrier layer 115 are not removed completely, leaving residue in the spaces 117 between the adjacent NS structures 101. The residue results from a process (e.g. etching) being unable to remove those sections due to a pinching off due to a close proximity (e.g. the small spaces 117) of the NS structures 101 to each other.
Adverting to FIG. 1F, a WF layer 121 is formed surrounding the annealed gate dielectric layer 119; however, the WF layer 121 is not formed on sections 123 of the annealed gate dielectric layer 119 in the spaces 117. The incomplete layer of the WF metal layer 121 around each NS structure 101 can negatively impact channel performance of the NS structures 101 and threshold voltage (Vt) controllability.
Therefore, a need exists for methodology enabling a pinch-off free annealing process for NS structures and the resulting devices.